1. Field of the Invention
The present invention relates to output driver circuits for semiconductor integrated circuit devices, and more particularly, to an output driver circuit allowing suppression of noise generation. The present invention also relates to a semiconductor integrated circuit device improved for burn-in testing. The present invention has particular applicability to a semiconductor memory device.
2. Description of the Background Art
In general, a plurality of semiconductor integrated circuit devices are mounted on a printed circuit board. The input and output terminals thereof are connected to each other via a wiring provided on the printed circuit board. When an output signal is provided from a semiconductor integrated circuit device, a wiring and another semiconductor integrated circuit device, i.e. load connected to that output terminal (or output lead) are driven by the output signal.
At the output stage of a semiconductor integrated circuit device, an output driver circuit is provided for driving the load connected to an output terminal. A large capacitance load or a small capacitance load may be connected to the same output driver depending on the applications. The transistor of the final stage of an output driver circuit generally has a large mutual conductance (or current driving capability) so as to drive the large capacitance load quickly.
The present invention is generally applicable to an output driver circuit provided at an output stage of a semiconductor integrated circuit device. In the following, an application to a dynamic random access memory (referred to as "DRAM" hereinafter) will be described.
FIG. 25 is a circuit diagram of a conventional output buffer circuit (or an output driver circuit). An output buffer circuit 330 shown in FIG. 25 is disclosed in Japanese Patent Laying-Open No. 3-214669. Referring to FIG. 25, output buffer circuit 330 includes NMOS transistors 1, 2, 3 and 4 for driving a load 331 via an output terminal DQ, NAND gates 5 and 6, NOR gates 7, 8, 9 and 10, inverters 11 and 12, and resistors 13a, 13b, 14a and 14b.
NAND gates 5 and 6 and inverters 11 and 12 have an internal power supply voltage V.sub.CCI of 3.3V supplied from a voltage down converter not shown. NOR gates 7, 8, 9 and 10, and other circuits are applied with a power supply voltage V.sub.CCE of 5V. Therefore, each of NOR gates 7-10 have a level conversion function.
NAND gate 5 receives an enable signal .phi..sub.MA and a data signal Mo. NAND gate 6 receives an enable signal .phi..sub.MA and an inverted data signal /Mo.
FIG. 26 is a timing chart for describing the operation of output buffer circuit 330 of FIG. 25. Referring to FIGS. 25 and 26, data signals Mo and /Mo are provided at time t1 (FIG. 26(a)). At time t2, an enable signal .phi..sub.MA rises (FIG. 26(b)). Therefore, output buffer circuit 330 is enabled in response to a signal .phi..sub.MA.
At time t3 after the rise of a signal .phi..sub.MA, gate voltage V1 of transistor 1 rises (FIG. 26(c)). The gate voltage V2 of transistor 2 is maintained at low level. Gate voltage V3 of transistor 3 responds to the rise of a signal .phi..sub.MA to rise at time t4 (FIG. 26(d)). The gate voltage V4 of transistor 4 is maintained at low level.
The difference in the rising timings of gate voltages V1 and V3 is determined by the difference in the resistances of delay resistors 14a and 13a. More specifically, the resistance of resistors 14a and 13a are determined so that the gate voltage V3 is delayed by approximately 1 nsec from the rise of the gate voltage V1. Therefore, in response to the rise of gate voltage V1, transistor 1 conducts at time t3. Transistor 3 responds to the rise of gate voltage V3 to conduct at time t4.
Transistor 1 has a channel width smaller than that of transistor 3. Therefore, the mutual conductance gm1 of transistor 1 is smaller than the mutual conductance gm3 of transistor 3. Transistor 2 has a channel width narrower smaller than that of transistor 4. Therefore, the mutual conductance gm2 of transistor 2 is smaller than the mutual conductance gm4 of transistor 4.
In general, output terminal DQ has load 331 connected equivalently as shown in FIG. 25. Referring to FIG. 25, an inductance component 104 and a capacitance component 105 are shown as equivalent load 331. Inductance component 104 and capacitance component 105 are induced by input/output terminals (or input/output leads), a bonding wire, a wiring formed on a printed circuit board, and other semiconductor integrated circuit devices directly connected to output terminal DQ.
Semiconductor integrated circuit devices such as semiconductor memories are used for various applications in various electronic equipments. This means that output terminal DQ has various semiconductor integrated circuit devices connected thereto. Therefore, output buffer circuit 330 shown in FIG. 25 has problems set forth in the following according to the size of the load capacitance connected to output terminal DQ.
Referring to FIG. 26(e), when the load capacitance component 105 is small, the small transistor 1 thoroughly charges the load capacitance component 105 before the large transistor 3 conducts at time t4. Therefore, a moderate rise time of output voltage DQ can be obtained at FIG. 26(e).
Here, if resistors 13a and 14a of FIG. 25 have the same resistance, the gate voltage V3' of transistor 3 rises at time t3 as shown by a chain dotted line in FIG. 26(d). In other words, transistors 1 and 3 conduct simultaneously. This means that the small load capacitance component 105 is charged by the two transistors 1 and 3 so fast as to cause ringing as shown in FIG. 26(f). More specifically, electromotive force L.multidot.di/dt is generated in inductance component 104, whereby ringing is induced in a resonation circuit formed by inductance component 104 and capacitance component 105. Because the amplitude of this ringing is increased as the electromotive force L.multidot.di/dt becomes higher, a noise of a high level is generated by the simultaneous conduction of the two transistors 1 and 3.
When the capacitance component 105 of the load is small, it is necessary to set resistors 13a and 14a so that transistors 1 and 3 conduct at different timing. However, when capacitance component 105 of the load is large, such a setting will induce a problem as shown in FIG. 26(g).
When capacitance component 105 of the load is great, the charging of capacitance component 105 is initiated by conductance of transistor 1. However, because transistor 1 has a small mutual conductance gm1, capacitance component 105 can not be charged sufficiently just by the conduction of transistor 1. Therefore, capacitance component 105 will be thoroughly charged after conduction of transistor 3 at time t4. As a result, the rise of output voltage DQ is delayed as shown in FIG. 26(g).
When capacitance component 105 of the load is high, it is necessary to set resistors 13a and 14a to have the same resistance to obtain simultaneous conduction of transistors 1 and 3. This allows a fast rise of output voltage DQ as shown in FIG. 26(e) even if capacitance component 105 of the load is large.
From the foregoing, it is appreciated that resistors 13a, 14a (and 13b, 14b) having different resistances must be used according to the level of the capacitance component of the load in a semiconductor integrated circuit device in order to suppress generation of noise such as ringing. To satisfy this requirement, the semiconductor manufacturer must provide a semiconductor integrated circuit device having a resistance differing only in the output buffer circuit with the same circuit configuration. This means that two production lines are required for the manufacture of similar products, resulting in increase of the manufacturing cost.
Next, we move on to a problem concerning high voltage generating circuits which drive output drivers. A conventional integrated circuit device having a plurality of output buffer circuits is supplied with one high voltage generating circuit for providing high voltage to output buffer circuits. A level clamp circuit is used to limit the level of high voltage. An output buffer consumes high voltage only when it outputs "H" data. If the high voltage generating circuit is designed so that all the output buffer circuits simultaneously provide data "H", large amount of high voltage charge will be wasted by the level clamp circuit when all the output buffer circuits output data "L". In order to save operating power, we differentiate the power supplying capability of the high voltage generating circuit according to the number of output data "H".
Finally we describe a problem which arises during burn-in test. Usually, we let semiconductor integrated circuits operate at high supply voltage under high temperature to screen defective devices out of manufactured devices before shipment. This procedure is called burn-in test. However, a conventional semiconductor integrated circuit device with a high voltage generating circuit has its internal circuit easily damaged due to excessive high voltage generation when burn-in testing is carried out. Therefore, a high voltage having a desired high level could not be supplied as power supply voltage V.sub.CC during burn-in testing. Therefore, a desired burn-in testing could not be carried out.